1. Field of the Invention
The present invention relates generally to data transfers in systems, and in particular, relates to improving bus efficiency by reducing the number of direct memory access (DMA) transfers to read data from memory with a scatter gather descriptor-based bus-mastering controller.
2. Background Information
In computer systems, components are coupled to each other via one or more busses. A variety of components can be coupled to the bus, thereby providing intercommunication between all of the various components/devices. An example of a bus that is used for data transfer with a processor or for data transfer between a memory and another device is the peripheral component interconnect (PCI) bus.
In order to relieve a processor of the burden of controlling the movement of blocks of data inside of a computer, direct memory access (DMA) transfers are commonly used. With DMA transfers, data can be transferred from one memory location to another memory location, or from a memory location to an input/output (I/O) device (and vice versa), without having to go through the processor. Additional bus efficiency is achieved by allowing some of the devices connected to the PCI bus to be DMA masters.
When transferring data using DMA methods, scatter gather descriptors are often used. High performance I/O controllers, such as gigabit Ethernet media access control (MAC) network controllers, are typically scatter gather descriptor-based bus-mastering devices that allow a computer to communicate with a network. The scatter gather descriptors are used to provide address and control information about data buffers (or xe2x80x9cscatter gather elementsxe2x80x9d) in memory that the controller needs to read or write for I/O operations. For example, the descriptors provide information such as the memory location from where bytes of data are to be moved, the address to where the bytes should go, the number of bytes to move, etc.
To read a data buffer using DMA transfers, a driver for the controller fills in the descriptor with information, such as the data buffer""s address and length, along with other control information. The controller then DMA transfers the descriptor from memory to a first-in-first-out (FIFO) buffer, for example, so that the controller can obtain the data buffer""s information (e.g., identify the data buffer""s memory location, length, etc.). After the controller has processed the descriptor to obtain this information, the controller can DMA transfer the contents/data in the data buffer referred to by the descriptor.
Accordingly, this scatter gather descriptor method uses at least two DMA transfers to read any data buffer (e.g., a DMA-transfer-to-data-buffer ratio of 2). Stated in another way, one overhead DMA transfer (to read the descriptor in the FIFO) is needed for each DMA transfer of data from the data buffer. Furthermore, each of these read operations can be split into multiple DMA transfers, thereby adding to the overhead. All of these overhead DMA transfers waste bus bandwidth and result in reduced performance.